La-e801p Rev 2.0 Schematic ((new)) -

Once ACOK is asserted high, the 3V/5V buck regulator activates, releasing +3VALW and +5VALW . The EC chip boots up using its internal code or by reading a portion of the shared SPI Flash. Step 3: Power Button Trigger

Fixing a "dead" or un-triggered LA-E801P board requires measuring components along the primary power rails in sequence. The structural schematic charts this precise progression:

The LA-E801P is built around the Intel processor series (7th Gen). Because this is a 2-in-1 convertible, the board is designed to handle frequent shifts in orientation, meaning the hinge and sensor connectors are critical points of failure often documented in the schematic. Key Components: CPU: Intel Core i3/i5/i7 (Soldered BGA). RAM: LPDDR3 (On-board, typically non-upgradable). la-e801p rev 2.0 schematic

), the EC assumes the laptop screen is closed and ignores the power button entirely.

Caps Lock light works, but screen remains black. Once ACOK is asserted high, the 3V/5V buck

Technicians working on the LA-E801P Rev 2.0 frequently report a few common failure points. When analyzing the schematic, make sure to cross-reference these sections first: The Input Protection Circuit

A: Use OpenBoardView (free, open source) or FlexBV (paid, professional). Do not use ancient DOS software. RAM: LPDDR3 (On-board, typically non-upgradable)

The LA-E801P Rev 2.0 Go to product viewer dialog for this item.

Here is a technical review of the schematic and board design from the perspective of an electronics engineer or hardware integrator.

: Pinouts for the detachable keyboard connector, M.2 SSD slots, and the display (eDP) interface. Common Uses for the Schematic